PIC32MX3XX/4XX
FIGURE 2-1:
RECOMMENDED
2.4
Master Clear (MCLR) Pin
MINIMUM CONNECTION
The MCLR pin provides for two specific device
functions:
V DD
C EFC
0.1 μF
Ceramic
C BP
? Device Reset
? Device Programming and Debugging
R
R1
MCLR
Pulling The MCLR pin low generates a device reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
C
PIC32MX
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
V SS
V DD
levels (V IH and V IL ) and fast signal transitions must
not be adversely affected. Therefore, specific values
0.1 μF
V DD
V SS
0.1 μF
of R and C will need to be adjusted based on the
application and PCB requirements.
Ceramic
C BP
10 Ω
0.1 μF
Ceramic
C BP
Ceramic
C BP
0.1 μF
Ceramic
C BP
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components shown in Figure 2-2 within
2.2.1
BULK CAPACITORS
one-quarter inch (6 mm) from the MCLR pin.
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 μF
to 47 μF. This capacitor should be located as close to
the device as possible.
FIGURE 2-2:
V DD
EXAMPLE OF MCLR PIN
CONNECTIONS
2.3 Capacitor on Internal Voltage
Regulator (V CAP /V DDCORE )
2.3.1 INTERNAL REGULATOR MODE
A low-ESR (< 1 Ohm) capacitor is required on the
V CAP /V DDCORE pin, which is used to stabilize the
R
JP
C
R1
MCLR
PIC32MX
internal voltage regulator output. The V CAP /V DDCORE
pin must not be connected to V DD , and must have a
C EFC capacitor, with at least a 6V rating, connected to
ground. The type can be ceramic or tantalum. Refer to
additional information on C EFC specifications. This
mode is enabled by connecting the ENVREG pin to
V DD .
2.3.2 EXTERNAL REGULATOR MODE
In this mode the core voltage is supplied externally
through the VDDCORE pin. A low-ESR capacitor of
10 μF is recommended on the V DDCORE pin. This mode
is enabled by grounding the ENVREG pin.
The placement of this capacitor should be close to the
V CAP /V DDCORE . It is recommended that the trace
length not exceed one-quarter inch (6 mm). Refer to
details.
DS61143G-page 32
Note 1:
2:
3:
R ≤ 10 k Ω is recommended. A suggested
starting value is 10 k Ω . Ensure that the MCLR
pin V IH and V IL specifications are met.
R1 ≤ 470 Ω will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
V IH and V IL specifications are met.
The capacitor can be sized to prevent uninten-
tional resets from brief glitches or to extend the
device reset period during POR.
? 2010 Microchip Technology Inc.
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